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DATA SHEET
MOS INTEGRATED CIRCUIT
PD3777
5400 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
The PD3777 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The PD3777 has 3 rows of 5400 pixels, and each row has a double-sided readout type of charge transfer register. And it has reset feed-through level clamp circuits, a clamp pulse generation circuit and voltage amplifiers. Therefore, it is suitable for 600 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
* Valid photocell * Photocell size * Line spacing * Color filter * Resolution : : 5400 pixels x 3 : 5.25 x 5.25 m
2
* Photocell's pitch : 5.25 m : 42 m (8 lines) Red line - Green line, Green line - Blue line : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx*hour) : 24 dot/mm A4 (210 x 297 mm) size (shorter side) 600 dpi US letter (8.5" x 11") size (shorter side)
7
* Drive clock level : CMOS output under 5 V operation * Data rate * Power supply * On-chip circuits : : : 4 MHz MAX. : +12 V : Reset feed-through level clamp circuits Clamp pulse generation circuit Voltage amplifiers
ORDERING INFORMATION
Part Number Package CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
PD3777CY
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S14583EJ1V0DS00 (1st edition) Date Published December 1999 NS CP (K) Printed in Japan
(c)
1999
S5399
VOUT1 (Blue)
21
........
Photocell (Blue)
S5400
D14
D64
D65
D66
Transfer gate CCD analog shift register
Data Sheet S14583EJ1V0DS00
CCD analog shift register Transfer gate
S5399
D67
S1
S2
VOUT2 (Green)
22
........
Photocell (Green)
S5400
D14
D64
D65
D66
Transfer gate CCD analog shift register
CCD analog shift register Transfer gate
S5399
D67
S1
S2
VOUT3 (Red)
1
........
Photocell (Red)
S5400
D14
D64
D65
D66
Transfer gate Clamp pulse generator CCD analog shift register
D67
S1
S2
2
BLOCK DIAGRAM
VOD 19
2L
17
GND 2
GND 11
1
14
CCD analog shift register Transfer gate 13
TG1 (Blue)
12
TG2 (Green)
10
TG3 (Red)
PD3777
3
4
9
2
RB
1L
PD3777
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) * PD3777CY
Output signal 3 (Red) Ground Reset gate clock Last stage shift register clock 1 No connection No connection No connection No connection Shift register clock 2 Transfer gate clock 3 (for Red) Ground
VOUT3 GND
1 2
22 21
VOUT2 VOUT1 NC VOD NC
Output signal 2 (Green) Output signal 1 (Blue) No connection Output drain voltage No connection Last stage shift register clock 2 No connection No connection Shift register clock 1 Transfer gate clock 1 (for Blue) Transfer gate clock 2 (for Green)
1
1
RB 1L
NC NC NC NC
3 4 5 6
1
20 19 18 17 16 15 14 13 12
Green
Blue
Red
2L
NC NC
7 8 9 10 11
2
1 TG1 TG2
5400
5400
GND
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
5.25 m 2.75 m 2.5 m
5400
TG3
Blue photocell array 8 lines (42 m)
5.25 m
5.25 m Channel stopper
Green photocell array 8 lines (42 m)
5.25 m Aluminum shield
Red photocell array
Data Sheet S14583EJ1V0DS00
3
PD3777
ABSOLUTE MAXIMUM RATINGS (TA = +25 C)
Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Transfer gate clock voltage Operating ambient temperature Storage temperature VOD V 1, V 2, V 1L, V 2L V RB V TG1 to V TG3 TA Tstg Symbol Ratings -0.3 to +15 -0.3 to +8 -0.3 to +8 -0.3 to +8 -25 to +60 -40 to +70 Unit V V V V C C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 C)
Parameter Output drain voltage Shift register clock high level Shift register clock low level Reset gate clock high level Reset gate clock low level Transfer gate clock high level Transfer gate clock low level Data rate VOD V 1H, V 2H, V 1LH, V 2LH V 1L, V 2L, V 1LL, V 2LL V RBH V RBL V TG1H to V TG3H V TG1L to V TG3L f RB Symbol MIN. 11.4 4.5 -0.3 4.5 -0.3 4.5 -0.3 - TYP. 12.0 5.0 0 5.0 0
Note V 1H
MAX. 12.6 5.5 +0.5 5.5 +0.5
Note V 1H
Unit V V V V V V V MHz
0 1.0
+0.5 4.0
Note When Transfer gate clock high level (V TG1H to V TG3H) is higher than Shift register clock high level (V 1H), Image lag can increase.
4
Data Sheet S14583EJ1V0DS00
PD3777
ELECTRICAL CHARACTERISTICS
TA = +25 C, VOD = 12 V, data rate (f RB) = 1 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter Saturation voltage Saturation exposure Red Green Blue Photo response non-uniformity Average dark signal Dark signal non-uniformity Power consumption Output impedance Response Red Green Blue Image lag Offset level
Note 1 Note 2
Symbol Vsat SER SEG SEB PRNU ADS DSNU PW ZO RR RG RB IL VOS td TTE RI Red Green Blue
Test Conditions
MIN. 2.0
TYP. 2.5 0.420 0.429 0.739
MAX. -
Unit V lx*s lx*s lx*s
VOUT = 1.0 V Light shielding Light shielding
6 0.2 1.5 360 0.5 4.15 4.07 2.36 5.94 5.82 3.38 2.0 4.0 5.5 50 92 0 98 1.0 630 540 460
20 2.0 5.0 540 1 7.72 7.57 4.39 7.0 7.0
% mV mV mW k V/lx*s V/lx*s V/lx*s % V ns %
VOUT = 1.0 V
Output fall delay time
VOUT = 1.0 V VOUT = 1.0 V, data rate = 4 MHz VOUT = 1.0 V
Total transfer efficiency Register imbalance Response peak
4.0
% nm nm nm times times
Dynamic range
Note 1
DR1 DR2
Vsat/DSNU Vsat/ Light shielding Light shielding -1000 -
1666 2500 -300 1.0 +500 -
Reset feed-through noise Random noise
RFTN
mV mV
Notes 1. Refer to TIMING CHART 2. . 2. When each fall time of 1L and 2L (t2', t1') is the TYP value (refer to TIMING CHART 2).
Data Sheet S14583EJ1V0DS00
5
PD3777
INPUT PIN CAPACITANCE (TA = +25 C, VOD = 12 V)
Parameter Shift register clock pin capacitance 1 Shift register clock pin capacitance 2 Last stage shift register clock pin capacitance Symbol C 1 C 2 C L Pin name Pin No. 14 9 4 17 3 13 12 10 MIN. TYP. 650 650 10 10 10 60 60 60 MAX. Unit pF pF pF pF pF pF pF pF
1 2 1L 2L RB TG1 TG2 TG3
Reset gate clock pin capacitance Transfer gate clock pin capacitance
C RB C TG
6
Data Sheet S14583EJ1V0DS00
TIMING CHART 1 (for each color)
TG1 to TG3
1 2 3 4 5 6 7
1 2 1L 2L
Data Sheet S14583EJ1V0DS00
RB
VOUT1 to VOUT3
Optical black (49 pixels) Invalid photocell (2 pixels)
Valid photocell (5400 pixels) Invalid photocell (3 pixels)
Note Input the RB pulse continuously during this period, too.
5463 5464 5465 5466 5467 5468 5469
Note
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 61 62 63 64 65 66
8
Note
PD3777
7
8
TIMING CHART 2 (for each color)
t1 t2
1
90 % 10 %
2
90 % 10 % t1' t2'
1L
Data Sheet S14583EJ1V0DS00
90 % 10 %
2L
t5 t6
90 % 10 % t3 t4
RB
90 % 10 %
+
td RFTN td
VOUT VOS 10 %
_
RFTN 10 %
PD3777
PD3777
TG1 to TG3, 1, 2 TIMING CHART
t8 90 % t7 t9
TG1 to TG3
10 % t10 90 % t11
1
2
Symbol t1, t2 t1', t2' t3 t4 t5, t6 t7 t8, t9 t10, t11
MIN. 0 0 20 130 0 3000 0 900
TYP. 50 5 150 300 50 10000 50 1000
MAX. - - - - - - - -
Unit ns ns ns ns ns ns ns ns
1, 2 cross points
1
2 V or more
2 V or more
2
1L, 2 cross points
2
2 V or more
1L
0.5 V or more
1, 2L cross points
1
2 V or more
2L
0.5 V or more
Remark Adjust cross points ( 1, 2), ( 1L, 2) and ( 1, 2L) with input resistance of each pin.
Data Sheet S14583EJ1V0DS00
9
PD3777
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula.
x x 100 x x : maximum of xj - x
5400 j=1
PRNU (%) =
xj
x=
5400
xj : Output voltage of valid pixel number j
VOUT
Register Dark DC level
x x
4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
5400 j=1
dj
dj : Dark signal of valid pixel number j
ADS (mV) =
5400
10
Data Sheet S14583EJ1V0DS00
PD3777
5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of dj - ADS j = 1 to 5400 dj : Dark signal of valid pixel number j
VOUT ADS Register Dark DC level DSNU
6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx*s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line.
TG
Light ON OFF
VOUT V1 VOUT
IL (%) =
V1 VOUT
x 100
9. Register imbalance : RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels.
n 2
2 n RI (%) =
(V2j - 1 - V2j)
j=1
1 n
Vj
j=1
n
x 100
n : Number of valid pixels Vj : Output voltage of each pixel
Data Sheet S14583EJ1V0DS00
11
PD3777
10. Random noise : Random noise is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling at dark (light shielding).
100
(mV) =
i=1
(Vi - V)
100
2
, V=
1
100
100 i = 1
Vi
Vi : A valid pixel output signal among all of the valid pixels for each color
VOUT V1 V2 line 1 line 2
V100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
...
line 100
...
12
Data Sheet S14583EJ1V0DS00
PD3777
STANDARD CHARACTERISTIC CURVES (Nominal)
DARK OUTPUT TEMPERATURE CHARACTERISTIC
8 2
STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25 C)
4
Relative Output Voltage
2
1
0.5
Relative Output Voltage
10 20 30 40 50
1
0.25
0.2
0.1 0
0.1
1
5 Storage Time (ms)
10
Operating Ambient Temperature TA(C)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25 C)
100 R
B 80
G
Response Ratio (%)
60
40
G 20
B 0 400 500 600 Wavelength (nm) 700 800
Data Sheet S14583EJ1V0DS00
13
PD3777
APPLICATION CIRCUIT EXAMPLE
+5 V 10 + 10 F/16 V 0.1 F B3 1 2 47 150 3 4 5 NC 6 7 8 NC 4.7
2
+12 V
+
PD3777
VOUT3 GND
RB 1L
0.1 F 47 F/25 V 22 21 20 19 18 17 16 15 NC
1
VOUT2 VOUT1 NC VOD NC
2L
B2 B1 +
+5 V
RB
0.1 F 10 F/16 V
150
NC NC
NC
9 10 11
2 TG3
14 13 12
4.7 10
1 TG
10
TG1 TG2
10
GND
Remark The inverters shown in the above application circuit example are the 74HC04 (data rate < 2 MHz) or the 74AC04 (data rate: 2 to 4 MHz).
B1 to B3 EQUIVALENT CIRCUIT 12 V + 100 CCD VOUT 100 2SC945 47 F/25 V
2 k
14
Data Sheet S14583EJ1V0DS00
PD3777
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400))
(Unit : mm) 1bit 0.50.3
37.5 44.00.3
9.250.3
2.0
10.16
(1.79)
2.550.2 1 1.020.15 0.460.1 25.4 2.54 (5.42) 4.210.5 4.390.4
0 10
0.25 0.05
Name Plastic cap
Dimensions 42.9 x 8.35 x 0.7
2
Refractive index 1.5
1 The bottom of the package
The surface of the chip
2 The thickness of the cap over the chip 22C-1CCD-PKG6-1
Data Sheet S14583EJ1V0DS00
15
PD3777
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "Semiconductor Device Mounting Technology Manual" (C10535E). Type of Through-hole Device
PD3777CY : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Process Partial heating method Conditions Pin temperature : 300 C or below, Heat time : 3 seconds or less (per pin)
Caution During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact.
16
Data Sheet S14583EJ1V0DS00
PD3777
[MEMO]
Data Sheet S14583EJ1V0DS00
17
PD3777
NOTES ON CLEANING THE PLASTIC CAP
1 CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches. The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used.
2 RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent.
Solvents Ethyl Alcohol Methyl Alcohol Isopropyl Alcohol N-methyl Pyrrolidone
Symbol EtOH MeOH IPA NMP
18
Data Sheet S14583EJ1V0DS00
PD3777
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S14583EJ1V0DS00
19
PD3777
[MEMO]
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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